automotiveci-cdtesting

How Vector's RocqStat acquisition changes release gating for real-time systems

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2026-02-06 12:00:00

10 min read

Vector's RocqStat integration into VectorCAST makes timing analysis a CI/CD first-class citizen—learn practical gating strategies and timing-aware toggle tips.

Hook: Stop shipping regressions that only show up on the road

Production risktakers in real-time and automotive domains face a familiar, painful pattern: a feature passes unit and integration tests, is merged through CI/CD, then fails timing expectations on an ECU in the field. The result is emergency rollbacks, missed SLAs and costly re-certification cycles. With Vector's January 2026 acquisition of RocqStat and planned integration into VectorCAST, teams now have a path to build timing-aware CI/CD gates and tie feature toggles to verified timing budgets—if they change their pipelines and processes accordingly.

What the Vector–RocqStat deal means for release engineering

In early 2026 Vector Informatik announced the acquisition of StatInf’s RocqStat technology and team, signalling a focused effort to unify WCET (worst-case execution time) analysis and software verification within the VectorCAST toolchain. The public rationale: incorporate advanced timing analysis directly into mainstream verification workflows so timing safety gets treated as code-quality, not an afterthought.

“Vector will integrate RocqStat into its VectorCAST toolchain to unify timing analysis and software verification” — Automotive World, Jan 16, 2026

This integration matters for release engineering because it makes detailed timing analysis available inside CI/CD loops rather than being relegated to periodic offline slides. That changes what qualifies as a gate and how feature toggles are used for staged rollouts.

Why timing analysis belongs in CI/CD gates for real-time systems

Real-time systems don’t just need correct behavior—they must meet timing contracts. A late control loop cycle can be as harmful as a logic bug. Typical testing gaps include:

Lack of automated WCET regression checks in PRs.
Feature toggles enabled in production without timing budgets documented or validated.
Multicore interference and shared bus effects that show up only in system integration.

Embedding timing analysis into CI/CD addresses those gaps by making timing a first-class verification artifact: timing budgets, traces and WCET estimates become part of the release decision.

2026 context and trends

Software-defined vehicles and ECU consolidation increase per-execution complexity, raising timing-analysis needs (late 2025–early 2026 trend).
Tool consolidation: vendors are integrating static and measurement-based timing tools into verification suites.
Regulatory scrutiny (safety and cybersecurity) pushes teams to produce machine-readable evidence—timing reports fit naturally.
Cloud orchestration for hardware-in-the-loop (HIL) and automated regression farms becomes mainstream, enabling scalable timing pipelines.

How integrated timing tools change CI/CD gates: principles

At a high level, integrating RocqStat-style timing analysis into CI/CD turns timing into an enforceable policy. The resulting gates should follow three principles:

Fast, actionable checks in pre-merge and PR pipelines for quick feedback (approximate WCET or timing regression indicators).
Deterministic full analysis in nightly or pre-release pipelines using measurement-based and static WCET tools on realistic hardware or high-fidelity simulators.
Production safety gates where feature toggle activation requires an associated timing contract and telemetry verification before global rollout.

Typical CI/CD gate tiers for timing

PR gate: Lightweight static timing checks and heuristics; fail fast on obviously regressive changes.
Merge gate: Full unit+integration tests plus a timing estimate produced by an accelerated RocqStat pass or cached partial analysis.
Nightly gate: Exhaustive WCET and interference analysis on representative targets (HIL/SIL) with artifacts stored for audit.
Release gate: Signed timing contract report and telemetry baseline; hard failure prevents release.

Practical gating strategies and policies

Below are usable, battle-tested strategies release engineers can apply when integrating timing analysis into gates.

1) Dual-threshold gating (warning vs fail)

Use two thresholds tied to the system timing budget: a soft threshold generates warnings and blocks merges only if other quality metrics degrade; a hard threshold fails the pipeline immediately. Example for a 10ms control loop:

Soft warning at 80% (8 ms).
Hard fail at 95% (9.5 ms).

This reduces false positives from measurement noise while keeping strict bounds.

2) Timing contracts for feature toggles

Attach a timing contract to any feature flag that affects control loops. The contract should state the expected WCET delta and monitoring SLOs. CI should reject merge if the claimed contract is missing or the change exceeds the budget.

3) Canary rollouts with timing telemetry

Enable toggles on a small subset of vehicles or ECUs and collect high-resolution timing telemetry. Automate rollback if percentile latency or missed cycles exceed thresholds. This ties release gating to real-system observability; consider on-device capture and low-latency telemetry pipelines for richer signals.

4) Progressive validation: from SIL to HIL

Run timing-emulation or SIL passes early and schedule hardware-in-the-loop runs at milestones. Automate test lab orchestration to reserve HIL time for pre-release exhaustive timing checks.

Example: Adding a RocqStat timing gate to a GitLab CI pipeline

Below is a compact example showing how a timing tool integrated into VectorCAST could be invoked in CI. The pipeline runs a quick estimate on PRs and fails if the estimated WCET exceeds the soft threshold. This is pseudocode adapted for a typical CLI-based timing tool integration.

stages:
  - build
  - test
  - timing

quick_timing_check:
  stage: timing
  script:
    - ./vectorcast/run_tests.sh --pr
    - ./rocqstat-cli analyze --project build/artefacts --mode quick --output timing.json
    - python3 scripts/check_timing.py timing.json --soft 8.0 --hard 9.5
  artifacts:
    paths:
      - timing.json
  only:
    - merge_requests

The check_timing.py script parses the timing.json and exits with code 0 (pass), 1 (warning) or 2 (fail). The CI policy treats exit code 2 as a hard failure.

Sample check_timing.py (concept)

import json, sys

with open('timing.json') as f:
    data = json.load(f)

wcet_ms = data['wcet_ms']

soft = float(sys.argv[1])
hard = float(sys.argv[2])

if wcet_ms >= hard:
    print(f"HARD FAIL: WCET {wcet_ms}ms >= {hard}ms")
    sys.exit(2)
elif wcet_ms >= soft:
    print(f"WARNING: WCET {wcet_ms}ms >= {soft}ms")
    sys.exit(1)
else:
    print(f"PASS: WCET {wcet_ms}ms below {soft}ms")
    sys.exit(0)

Feature toggles: make them timing-aware

Feature toggle systems are invaluable for staged rollouts, but in real-time systems they become dangerous if they change execution paths unpredictably. Practical controls:

Store timing metadata in toggle definitions: expected WCET delta, test harness ID, required HIL tests.
Disallow toggle activation in production unless the feature's timing contract is signed off and recent telemetry is within SLOs.
Use policy-as-code to enforce timing preconditions before toggles become eligible for rollout.
Automate rollback of toggles when latency or missed deadline rates spike above the canary thresholds.

Example toggle metadata (JSON)

{
  "flag": "adaptive_cruise_new_gap_logic",
  "timing_contract_ms": 0.8,
  "tests_required": ["timing_sil_quick", "timing_hil_full"],
  "canary_policy": { "population": 0.05, "monitoring_window": "10m", "fail_on": { "deadline_miss_pct": 1.0 } }
}

Automating timing tests in your test pipeline

Tips to make timing automation robust and repeatable:

Isolate sources of nondeterminism: fix CPU frequency, disable power-saving, or pin cores to avoid variable thermal throttling.
Use repeatable workloads and seeds; collect statistically meaningful samples (p50, p90, p99, max).
Model interference explicitly for multicore targets—create synthetic co-runners to emulate worst-case bus contention.
Aggregate results and store artifactized timing reports for traceability and audits; consider scalable OLAP or time-series approaches when you persist artifacts.
Automate comparison with previous baselines, and produce a human-readable summary for triage owners.

Multicore ECUs, shared resources and the limits of naive WCET

One of RocqStat's strengths is marrying static analysis with measurement-based insights—critical for multicore ECUs where interference can make static WCET pessimistic or optimistic if not modeled. Practical mitigations:

Use measurement-based interference injection to bound shared bus effects.
Employ mixed static/dynamic WCET: use static analysis for isolated execution paths and measurement-based analysis for interaction-heavy paths.
Introduce scheduling contracts (time partitioning, ARINC-653-style) to limit shared-resource unpredictability.

Case study: rolling out an adaptive cruise control change

Scenario: an algorithmic change in the distance-control loop adds additional computation. Here’s a distilled flow showing timing-aware gating and toggles:

Developer opens PR; quick RocqStat estimate runs in PR and flags a 10% WCET increase (soft warning).
Owner runs an extended analysis in a merge gate using full static + measurement-based WCET; the result is within the soft threshold but above the historical baseline.
Feature is merged behind a toggle with timing metadata and a canary rollout policy targeting 2% of fleet.
HIL runs overnight produce the signed timing contract and artifacts are saved in VectorCAST’s repository.
Canary vehicles collect telemetry. The pipeline continuously evaluates canary telemetry; after 48 hours everything is within SLOs and the toggle is progressively expanded.
If telemetry had exceeded the canary thresholds, the toggle would auto-roll back and open a blocking issue, preventing a global release until triage.

Regulatory and audit considerations

In safety-critical contexts (ISO 26262 and similar), timing evidence is required for many ASIL-rated functions. Key points:

Persist artifacts (timing reports, configuration, tool versions) as part of release artifacts; use signed storage and tamper-evidence so certification teams can trust the data.
Record toggle decisions and timestamps for when timing contracts were accepted or when canaries were started/stopped; enterprise playbooks for incident and evidence handling are relevant here.
Use signed, tamper-proof artifacts when passing evidence to certification teams — treat evidence the way high-risk incident teams treat critical logs and artifacts (enterprise playbooks provide useful process analogies).

Observability: from traces to actionable SLOs

Timing telemetry in production must be granular enough to detect deadline misses and attribute them to features or environmental factors. Practical metrics:

Deadline miss rate (per interval)
Pxx latency percentiles (p50/p90/p99)
WCET estimate trends over build history
Toggle-enabled vs toggle-disabled comparative histograms

Build dashboards that correlate toggles to timing regression signals and automate alerts for early action; pair these dashboards with robust on-device or low-latency capture pipelines (on-device capture) to reduce telemetry blind spots.

Implementation checklist: turning timing analysis into enforceable gates

Baseline: Establish current WCET and percentiles on representative hardware.
Integrate: Add RocqStat or equivalent into CI with quick/fast/complete tiers.
Policy: Define soft/hard thresholds and map them to CI exit codes.
Toggle design: Require timing metadata on flags and enforce gating in the toggle management system.
Automation: Orchestrate SIL and HIL runs, and persist artifacts to an immutable store.
Telemetry: Ship high-resolution timing telemetry and implement canary rollback automation.
Audit: Retain signed timing contracts and test traces for compliance.

Practical thresholds and examples

Thresholds must be tuned to your system; sample starting points for a control loop target of 10ms:

Soft warning: 75–85% of loop budget.
Hard fail: 90–97% depending on safety margin and redundancy.
Canary fail: absolute deadline misses > 0.5% over a monitoring window or p99 latency > hard threshold.

Adjust thresholds based on historical variability and worst-case environmental scenarios.

Future predictions (2026 and beyond)

Timing-as-code: Expect to see timing contracts checked in as code with CI hooks by late 2026.
Policy-as-code for toggles: automatic enforcement of timing preconditions at feature-flag platforms; modern devtool approaches and resilient front-end patterns inform how policy automation may look (developer tooling analogies).
ML-assisted WCET: tools will use ML to predict interference patterns and propose guardrails — an active area of research and tooling.
Standardization pressure: industry groups will publish guidelines for timing in CI/CD for safety-critical domains.

Actionable takeaways

Start small: add a lightweight timing estimate to PRs today—catching regressions early is cheap and high-value.
Use two-threshold gates to balance noise and safety.
Treat feature toggles as first-class citizens in timing policies—embed timing metadata and enforce canary checks.
Automate HIL orchestration for nightly or pre-release exhaustive timing analysis.
Store and sign timing artifacts for auditability and certification; scalable data and storage approaches can help when you need long-term retention.

Closing: why this matters now

Vector’s acquisition of RocqStat is part of a broader 2025–2026 trend: timing analysis moving from offline specialist activity into the core of release engineering. For teams building real-time and automotive systems, integrating timing verification into CI/CD and feature toggle workflows is now achievable and strategically essential. When timing becomes an automated gate and toggle lifecycles are tied to verifiable timing contracts, deployments get safer, rollbacks get faster and certification evidence becomes a by-product of your pipeline rather than a late-stage scramble.

Call to action

If you are responsible for release engineering, set up a short pilot this quarter: add a PR-level timing check, attach timing metadata to one critical feature toggle, and run a canary with automated telemetry checks. Need help? Contact toggle.top for a hands-on workshop—transform your CI/CD gates into timing-aware release controls and reduce your deployment risk in production real-time systems.

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